MIT’s new 3D chip design could be the key to powerful edge computing

MIT researchers have developed a new 3D chip fabrication method that uses carbon nanotubes and resistive random-access memory (RRAM) cells together to create a combined nanoelectronic processor design that supports complex, 3D architecture – where traditional silicon-based chip fabrication works with 2D structures only.

The 3D design is possible because these carbon nanotube circuits and RRAM memory components can be made using temperatures below 200 degrees Celsius, which is far, far less than the 1,000 degree temps needed to fabricate today’s 2D silicon transistors. Lower temperatures mean you can build an upper layer on top of another without damaging the one or ones below.

The reason a 3D construction model works so well is that it provides an opportunity to make small processors much better at processing huge amounts of data – in volumes that would otherwise necessitate a round-trip to a data center or processor farm. More and more, scientists and product designers are looking to do advanced data processing ‘at the edge,’ meaning locally where sensors are located, since round-tripping data even at bandwidth speeds is a risk and, in some cases, impossible in applications including autonomous driving.

The design is also unique in that it can combine on a single chip the logic and memory components of a processor in one, and both the carbon nanotube logic portions and the RRAM components are more energy-efficient than either silicon or DRAM are today. Carbon nanotubes can also act as sensors, so the top layer can be a sensor, too, feeding data to the rest of the chip for processing and storage.

One expert cited by MIT said that this could be the answer to continuing the exponential scaling of computer power in keeping with Moore’s Law, as traditional chip methods start to run up against physical limits. It’s still very early days, but a promising direction for future research and development for sure.